Memory chip

The CAT1021 is a comprehensive memory and supervisory management solution for microcontroller-based systems. An EEPROM serial 2-Kb I2C CPU supervisor is integrated with a system power supervisor with brown-out protection using low-power CMOS technology. The memory interface is via a 400 kHz I²C bus. The CAT1021 provides a precision VCC sensing circuit and two open-drain outputs: one (reset) output drives high and the other (reset) output drives low when VCC is below the reset threshold voltage. The CAT1021 also has a write protect input (WP). If WP is tied to logic high, write operations are disabled. The supervisor has a 1.6-second watchdog timer circuit that resets the system to a known state if a software or hardware failure causes the system to shut down or halt. A supervisory timer monitors the SDA signal. A power monitor and reset circuit protects the memory and system controller during power-on/off and under-voltage conditions. Five reset threshold voltages support 5.0 V, 3.3 V, and 3.0 V systems. If the supply voltage is out of tolerance, a reset signal is activated, preventing operation of the system microcontroller, ASIC or peripherals. The reset signal is typically deasserted 200 ms after the supply voltage exceeds the reset threshold level. When both high and low reset signals are active, interfacing with microcontrollers and other integrated circuits is simplified. Additionally, a reset pin or a separate input MR can be used as an input with push-button manual reset. The on-chip 2 Kb EEPROM memory has a 16-byte page. In addition, VCC sensing circuitry provides hardware data protection to prevent memory writes when VCC falls below the reset threshold or when VCC reaches the reset threshold during power-up. Available packages include 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin TDFN, and 8-pin MSOP. TDFN package