RTC clock synchronization buffer driver delay chip

The MC100EP14 is a low-skew 1:5 differential driver designed with clock distribution in mind to combine two clock sources into one input multiplexer. The ECL/PECL input signal can be differential or single-ended (if VBB output is used). The HSTL input can be used when the LVEP14 is run under PECL conditions. The EP14 specifically guarantees low output-to-output skew. Optimal design, layout, and handling minimize skew within and between devices. To ensure tight skew specifications are met, both ends of the differential output need to be terminated, even if only one output is used. If the output pair is not used, both outputs can be left open (unterminated) without affecting the skew ratio. The common enable (ENbar) is synchronous and the output is enabled/disabled in a low state. This avoids runt clock pulses when enabling/disabling the device, which can occur in asynchronous control. The internal flip-flops are locked on the falling edge of the input clock, so all relevant specification limits are referenced to the negative edge of the clock input. Only the VBB pin, the internally generated supply voltage, is provided for this device. For the single-ended input case, connect the unused differential input to VBB as the switch reference voltage. VBB can also re-bias AC-coupled inputs. When used, VBB and VCC are decoupled with 0.01 uF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use.